This invention relates to the provision of on-gate contacts for MOS components.
FIG. 1 shows a schematic diagram of a conventional MOS RF transistor 100 formed in a region 101 of a semiconductor substrate. The gate 102 extends across the width of a channel and the contacts 103 to the gate are located to one side of the region 101 over the thick (or field) oxide around the device. Source and drain contacts 104 are provided to the semiconductor substrate.
Conventional MOS transistor design forbids the placement of gate contacts over the channel as poor control of the etch process may consume a portion of the gate and in particular the highly conductive silicide top layer. This over-etching may expose the less conductive part of the gate to charging during the contact etch process leading to an increased electrical potential at the bottom of the contact, potentially causing local damage to the gate. Furthermore, as seen in FIG. 1, the contact size is generally larger than the drawn gate length, thereby preventing placement of contacts on the gate over the channel. All conventional MOS transistors therefore locate the gate contact away from the channel, over the thick field oxide where there will be no effect on the device.
As gate lengths decrease, the resistance of the gate increases and may affect the RF performance of the transistor. In particular, as the gate resistance increases, and the channel resistance decreases, the gate noise limits the noise figure of the device. It would therefore be desirable to decrease the sheet resistance of the gate electrode for new technology nodes. In practice however process integration choices may force the gate electrode to become significantly more resistive. As features sizes decrease, low-noise amplifiers can no longer be designed with sufficiently low noise figures using conventional layouts due to the increase in gate resistance.
The gate resistance is dependent, inter alia, on the effective width of the gate. FIG. 2 shows a MOS transistor 200 in which the gate 202 extends over the field oxide at both ends and a contact 203 is made at both of those ends.
The gate resistance can also be reduced by reducing the width of the channel and increasing the number of fingers. However, this leads to an increase in parasitic capacitance and area overhead.
FIG. 3 shows a further transistor layout 300 in which dual contacts 303 are located at each end of the gate 302 to reduce the contribution of the contacts to the overall resistance.
The ability to reduce the gate resistance is therefore limited by the topology of the devices, the effect of changes on other parameters, and material properties. There is therefore a requirement for a technique to reduce the gate resistance in MOS devices.
The embodiments described below are not limited to implementations which solve any or all of the disadvantages discussed above.